ZYNQ7010 在线重配置 使用PS配置PL
首先PL端编译后生成重配置用的固件
write_cfgmem -format bin -interface SMAPx32 -loadbit {up 0x00000000 "/home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/top.bin" } -force -disablebitswap -file "/home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/topnew.bin"对应的路径和文件名请参考你自己的
然后运行：
write_cfgmem -format bin -interface SMAPx32 -loadbit {up 0x00000000 "/home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/top.bit" } -force -disablebitswap -file "/home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/topnew.bin"
Command: write_cfgmem -format bin -interface SMAPx32 -loadbit {up 0x00000000 "/home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/top.bit" } -force -disablebitswap -file /home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/topnew.bin
Creating config memory files...
INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 4 due to the use of interface SMAPX32.
Creating bitstream load up from address 0x00000000
Loading bitfile /home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/top.bit
Memory size is calculated to be 2 MB
Writing file /home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/topnew.bin
Writing log file /home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/topnew.prm
===================================
Configuration Memory information
===================================
File Format BIN
Interface SMAPX32
Size 2M
Start Address 0x00000000
End Address 0x001FFFFF
Addr1 Addr2 Date File(s)
0x00000000 0x001FCB9B Apr 25 14:57:38 2025 /home/chanra1n/ZYNQ7010/ZYNQ7010.runs/impl_1/top.bit
1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully紧接着将程序发送至PS端，运行：
fpgautilfpgautil: FPGA Utility for Loading/reading PL ConfigurationUsage: fpgautil -b <bin file path> -o <dtbo file path>Options: -b <binfile> (Bin file path) -o <dtbofile> (DTBO file path) -f <flags> Optional: <Bitstream type flags> f := <Full | Partial > -n <Fpga region info> FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in the Device Tree Default: <full> -s <secure flags> Optional: <Secure flags> s := <AuthDDR | AuthOCM | EnUsrKey | EnDevKey | AuthEnUsrKeyDDR | AuthEnUsrKeyOCM | AuthEnDevKeyDDR | AuthEnDevKeyOCM> -k <AesKey> Optional: <AES User Key> -r <Readback> Optional: <file name> Default: By default Read back contents will be stored in readback.bin file -t Optional: <Readback Type> 0 - Configuration Register readback 1 - Configuration Data Frames readback Default: 0 (Configuration register readback) -R Optional: Remove overlay from a live treeExamples:(Load Full bitstream using Overlay) fpgautil -b top.bit.bin -o can.dtbo -f Full -n full (Load Partial bitstream using Overlay) fpgautil -b rm0.bit.bin -o rm0.dtbo -f Partial -n PR0 (Load Full bitstream using sysfs interface) fpgautil -b top.bit.bin -f Full (Load Partial bitstream using sysfs interface) fpgautil -b rm0.bit.bin -f Partial(Load Authenticated bitstream through the sysfs interface) fpgautil -b top.bit.bin -f Full -s AuthDDR (Load Parital Encrypted Userkey bitstream using Overlay) fpgautil -b top.bit.bin -o pl.dtbo -f Partial -s EnUsrKey -k <32byte key value> (Read PL Configuration Registers) fpgautil -b top.bit.bin -r (Remove Partial Overlay) fpgautil -R -n PR0 (Remove Full Overlay) fpgautil -R -n fullNote: fpgautil -R is responsible for only removing the dtbo file from the livetree. it will not remove the PL logic from the FPGA region.
只加载bit文件：fpgautil -b top.bin -f Full
加载bit和设备树：fpgautil -b top.bin -o can.dtbo -f Full -n full
部分重配置：fpgautil -b top.bin -o top.dtbo -f Partial -n PR0
