21
2022
04

Xilinx FIFO和ILA学习

`timescale 1ns / 1ps
//-------------------------------------------------------
//Filename       ﹕ FIFO_TOP.v
//Author         ﹕ ChanRa1n
//Description    ﹕ Control FIFO IP
//Calledby       ﹕ Topmodule
//RevisionHistory﹕ 2022-03-23 15:58:19
//Revision       ﹕ 1.0
//Email          ﹕ chenyu@myfpga.cn
//Website        ﹕ https://www.myfpga.cn
//Copyright(c) 2018-2022, MYFPGA.CN, All right reserved
//-------------------------------------------------------

module FIFO_TOP (
    input   Sys_clk_in,
    input   Sys_rst_n
);

//Signal
reg  [7:0]  din;
reg  [0:0]  wr_en;
reg  [0:0]  rd_en;
wire [7:0]  dout;
wire [0:0]  full;
wire [0:0]  empty;
wire [25:0] probe0;

//Private
reg  [2:0]  State_now;
reg  [2:0]  State_next;
reg  [7:0]  Trans_counter;//实际使用255
wire        Flag_write_read;
wire        Flag_read_idle;
localparam  STATE_IDLE =3'b001;
localparam  STATE_WRITE=3'b010;
localparam  STATE_READ =3'b100;

assign Flag_write_read=State_now==STATE_WRITE && Trans_counter==255;
assign Flag_read_idle=State_now==STATE_READ && Trans_counter==255;

always @(posedge Sys_clk_in or negedge Sys_rst_n) begin
    if(~Sys_rst_n)begin
        State_now<=STATE_IDLE;
    end
    else begin
        State_now<=State_next;
    end
end

always @(posedge Sys_clk_in or negedge Sys_rst_n) begin
    if(~Sys_rst_n)begin
        State_next<=STATE_IDLE;
    end
    else begin
        case(State_now)
            STATE_IDLE:State_next<=STATE_WRITE;
            STATE_WRITE:State_next<=Flag_write_read?STATE_READ:State_next;
            STATE_READ:State_next<=Flag_read_idle?STATE_IDLE:State_next;
            default:State_next<=State_next;
        endcase
    end
end

always @(posedge Sys_clk_in or negedge Sys_rst_n) begin
    if(~Sys_rst_n)begin
        Trans_counter<=0;
    end
    else begin
        case(State_now)
            STATE_IDLE:Trans_counter<=0;
            STATE_WRITE:Trans_counter<=Trans_counter+1;
            STATE_READ:Trans_counter<=Trans_counter+1;
            default:Trans_counter<=Trans_counter;
        endcase
    end
end

always @(posedge Sys_clk_in or negedge Sys_rst_n) begin
    if(~Sys_rst_n)begin
        din<=0;
        wr_en<=0;
        rd_en<=0;
    end
    else begin
        case(State_now)
            STATE_IDLE:begin din<=0;wr_en<=0;rd_en<=0; end
            STATE_WRITE:begin din<=Trans_counter;wr_en<=1;rd_en<=0; end
            STATE_READ:begin din<=0;wr_en<=0;rd_en<=1; end
            default:begin din<=0;wr_en<=0;rd_en<=0; end
        endcase
    end
end

fifo_generator_0 fifo_generator_0_u(
    .clk    (Sys_clk_in  ),
    .srst   (~Sys_rst_n ),
    .din    (din  ),
    .wr_en  (wr_en),
    .rd_en  (rd_en),
    .dout   (dout ),
    .full   (full ),
    .empty  (empty)
);

assign probe0 [0:0]   = wr_en;
assign probe0 [1:1]   = rd_en;
assign probe0 [2:2]   = full;
assign probe0 [3:3]   = empty;
assign probe0 [11:4]  = din;
assign probe0 [19:12] = dout;
assign probe0 [22:20] = State_now;
assign probe0 [25:23] = State_next;

ila_0  inst_ila_0 (
    .clk    (Sys_clk_in),  
    .probe0 (probe0)
);

endmodule

实验效果:

image.png

相关问题:

异步FIFO的深度计算问题

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